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Timing Simulations:
ModelSim post synthesis simulation guide:
1. In the Quartus software, in the processing menu, point to Start and
click start analysis and synthesis.
2. On the Assignments menu, click Settings.
3. In the Category list, select Simulation under EDA Tool Settings.
4. In the Tool name list, specify simulation tool as ModelSim-Altera. (DO
NOT turn on Run gate level simulation automatically. Click OK.
Check in Tools -> Options -> EDA Tool Options that the Modelsim-Altera
path is ok, otherwise set it.
Compileperform
the design
again.analysis
In the and
processing
menu, point
to Compilation.
Start and
5 . 5.
If needed
the Timing
then Processing
-> Start
click
on
Then, Processing -> Start -> EDA Netlist Writer
Start EDA netlist writer.
Now you have two files in the folder: simulation/modelsim/ in your altera
working directory – (1) .vho (VHDL Output) file and (2) .sdo (Standard Delay
Format Output) file.
6.
vhdl
Tools
-> Run
Simulation
Gate Level.
6.To
Tocompile
compilethe
the
VHDL
Output
File
(.vho), Tool
open ->
modelsim
and on compile
menu,
click will
compile.
7.
Modelsim
open and compile the .vho file.
7. Search up for the .vho file you generate with Altera Quartus and
compile it and click done.
8. In the Simulate menu click start simulation.
9. Click sdf tab and click add.
10. Browse for the .sdo file you created along with .vho using Altera
Quartus. Click ok.
11. In the Design menu, In the Name list, click the + icon to expand the
work directory and simulate the design entity that corresponds to the sdo
file.
12.You
Click
This the
will
simulatebyyour
design
and you or
will
be able ato
see
your
12.
canOK.
perform
simulation
creating
waveforms
by building
test
bench.
input output ports in the object window.
13. You can now add the signals to the wave and type "run XYZns".
This will generate waveforms with timing information. You can force
particular inputs to 0 or 1 values and type "run ABCns" again to see the
difference.
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