Elettronica Analogica
e Digitale (part 1)
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Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
D
n+
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RETI COMBINATORIE
Algebra booleana: logica binaria (a due stati)
A è una variabile booleana: A=1 oppure A=0
Funzioni logiche elementari per l’algebra
Booleana: AND, OR, NOT
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Logica positiva: livello di tensione + elevato
corrisponde all’1 logico;
livello di tensione + basso
corrisponde allo 0 logico;
Logica negativa: livello di tensione + elevato
corrisponde allo 0 logico;
livello di tensione + basso
corrisponde all’1 logico.
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PORTE LOGICHE
La porta NOT.
Out
In1
Out = NOT In1 = In1
In1
Out
0
1
1
0
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PORTE LOGICHE
La porta AND.
In1
Out
In2
Out = In1 AND In2 = In1 • In2
In1 In2
0
0
0
1
1
0
1
1
Out
0
0
0
1
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PORTE LOGICHE
La porta OR.
In1
Out
In2
Out = In1 OR In2 = In1 + In2
In1 In2
0
0
0
1
1
0
1
1
Out
0
1
1
1
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PORTE LOGICHE
La porta NAND.
In1
Out
In2
Out = In1 NAND In2 = In1 • In2
In1 In2
0
0
0
1
1
0
1
1
Out
1
1
1
0
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PORTE LOGICHE
La porta NOR.
In1
Out
In2
Out = In1 NOR In2 = In1 + In2
In1 In2
0
0
0
1
1
0
1
1
Out
1
0
0
0
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PORTE LOGICHE
La porta XOR.
In1
Out
In2
Out=In1 XOR In2=In1·In2+ In1·In2=In1⊕In2
In1 In2
0
0
0
1
1
0
1
1
Out
0
1
1
0
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PORTE LOGICHE
La porta XNOR.
In1
Out
In2
Out=In1 XNOR In2=In1·In2+ In1·In2=In1⊕In2
In1 In2
Out
0
0
1
0
1
0
1
0
0
1
1
1
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PROPRIETA’ FONDAMENTALI
NOT
AND
A + A=1
A • A=0
A • 0=0
A • 1=A
A • A=A
A • A=0
A=A
OR
A+0=A
A+1=1
A+A=A
A+A=1
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LEGGI DI DE MORGAN
A⋅ B ⋅C ⋅⋅⋅ = A + B + C + ⋅⋅⋅
A + B + C + ⋅⋅⋅ = A⋅ B ⋅C ⋅⋅⋅
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Inverter Voltage Transfer Characteristic
V(y)
V
f
OH
V(y)=V(x)
VM Switching Threshold
V OL
V OL
V
OH
V(x)
Nominal Voltage Levels
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Mapping logic levels to the voltage domain
V
“ 1”
V
OH
V
V
IH
out
Slope = -1
OH
Undefined
Region
V
“ 0”
V
Slope = -1
IL
V
OL
OL
V
IL
V
IH
V
in
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Definition of Noise Margins
"1"
V
OH
Noise margin high
NM H
V
IH
Undefined
Region
V
NM L
OL
V
IL
Noise margin low
"0"
Gate Output
Gate Input
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Regenerative Property
v0
v1
v2
v3
v4
v5
v6
A chain of inverters
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v
out
v3
v
out
v3
fin v(v)
f (v)
v1
v1
v3
fin v(v)
v2
v0
Regenerative
in
v
f (v)
v0
v2
in v
Non-Regenerative
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V (Volt)
5
v0
3
v1
1
2- 1
0
2
4
v2
6
8
10
t (nsec)
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Fan-in and Fan-out
N
Fan-out N
M
Fan-in M
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The Ideal Gate
V out
Ri = ∞
Ro = 0
Fanout = ∞
NMH = NML = VDD/2
g=∞
V in
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An Old-time Inverter
5.0
4.0
NM L
3.0
(
V
)
o
u
t
2.0
V
VM
NM H
1.0
0.0
1.0
2.0
3.0
V in (V)
4.0
5.0
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Delay Definitions
V in
50%
t
V out
tpHL
tpLH
90%
50%
t
10%
tf
tr
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A First-Order RC Network
R
vin
vout
C
tp = ln (2) τ = 0.69 RC
Important model – matches delay of inverter
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Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t +T
1 t +T
Pave = ∫
p (t )dt =
isupply (t )dt
∫
t
T t
T
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Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav × tp
Energy-Delay Product (EDP) =
quality metric of gate = E × tp
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A First-Order RC Network
R
vin
vout
CL
Vdd
T
T
E
= ∫ P ( t ) dt = V ∫ i
t dt = V
C dV
= C •V 2
0→1
dd sup ply( )
dd ∫
L out
L
dd
0
0
0
T
T
Vdd
1
2
E ca p = ∫ P cap ( t ) dt = ∫ V out i ca p( t )dt = ∫ C L Vout dVout = --- C • V dd
2 L
0
0
0
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